Name BB2_U34 ; PartNo 00 ; Date 20/1/2014 ; Revision 01 ; Designer Engineer ; Company FSC ; Assembly None ; Location ; Device g16v8 ; /* *************** INPUT PINS *********************/ PIN 1 = BMREQ_N; /* memory request from CPU */ PIN 2 = D_S; /* 0=select static memory (ROM/SRAM) 1=dynamic RAM */ PIN 3 = STDBB; /* 0=addresses onboard 1=addresses over the STD bus connector */ PIN 4 = BRD_N; /* read from CPU */ PIN 5 = BWR_N; /* write from CPU */ PIN 6 = BA15; PIN 7 = BA14; PIN 8 = BA13; PIN 9 = BA12; PIN 11 = BA11; /* *************** OUTPUT PINS *********************/ PIN 19 = !CHARCE_N; PIN 18 = !ATTCE_N; PIN 17 = !DYNOP_N; PIN 16 = !DYNWR_N; PIN 15 = !SMEMOP_N; PIN 14 = !DYNRD_N; PIN 13 = !SMEMRD_N; PIN 12 = !SMEMWR_N; /* *************** LOGIC ********************/ CHARCE_N = (!BA15 & BA14 & BA13 & !BA12) & !BMREQ_N & !D_S & !STDBB; ATTCE_N = (!BA15 & BA14 & BA13 & BA12) & !BMREQ_N & !D_S & !STDBB; DYNOP_N = !BMREQ_N & D_S & !STDBB & (!BRD_N # !BWR_N); DYNWR_N = !BMREQ_N & D_S & !STDBB & !BWR_N & BRD_N; SMEMOP_N = !BMREQ_N & !D_S & !STDBB & (!BRD_N # !BWR_N); DYNRD_N = !BMREQ_N & D_S & !STDBB & !BRD_N & BWR_N; SMEMRD_N = !BMREQ_N & !D_S & !STDBB & !BRD_N & BWR_N; SMEMWR_N = !BMREQ_N & !D_S & !STDBB & !BWR_N & BRD_N;