;-*- Mode:Text -*-

; Instruction set definition
; Bobp 7/16/86

64 bits, numbered 63..0, 0 is lsb and first in memory.
High bits of fields are in the highest-numbered bit positions.

Special cases of ICAT, NEXTPC and CHOP are decoded to form
branch-within-4K-page and call-within-cluster-zero.


Register addresses:

The register ram is addressed by 12 bits that are formed from a
six-bit DEST, LEFT, RIGHT or DRET field and either one of the
OPEN, ACTIVE or RETURN frame registers or the IMM field and the
IMMH register.  (IMMH is writable as a functional destination.)

Bits 5..4 of DEST, LEFT, RIGHT or DRET select the base frame:
	0	OPEN	bits 11..4 from OPEN
	1	ACTIVE	bits 11..4 from ACTIVE
	2	RETURN	bits 11..4 from RETURN
	3	GLOBAL	bits 11..8 from IMMH, 7..4 from IMM
Bits 3..0 are always become the register address bits 3..0.

If DRET indicates GLOBAL, no register location is written.

;;;;

Ordered by bit fields:

63:	STAT	Statistics flag.

62..61:		Spare.

60..58:	ICAT	Instruction Category.  Determines the meaning of the
		variable-use instruction fields.
		Values:
		0	ALU	ALUOP is 18..12;
				DRET is 36..34 and 3..0;
				11..0 is a ADDR, or SHIFT and MASK.
		1	ALUI	ALUOP is 31..25;
				IDATA is 15..0 or 23..0,
				depending on use of LEFT.
		2	LOADI	ALUOP is "Y<-R";
				IDATA is 31..0.
		3	ADDR	ALUOP is "Y<-R"; ADDR is 23..0.
				DRET is 36..32 and 24..23.
		4	ALUX	Same as ALU, but "alternate" ALUOP
				instruction space is selected.
		5	ALUIX	Same as ALUI, but "alternate" ALUOP.
		6,7		Reserved for floating-point.

57..56:	NEXTPC	Select PC for next instruction.
		Values:
		0	IR	All or part of ADDR is selected,
				as determined by ICAT and CHOP.
		1	DISP	ALU output register (OUT_REG) is
				selected as next PC.
		2	RPC	Return PC from call hardware is
				selected; required that CHOP be RETURN.
		3	NEXT	Current PC + 1 is selected.

55..54:	BOX	Boxed-data control for this ALU result and/or for
		MD and VMA registers.  For ALU (DEST is a register location),
		selects left-boxed-bit, right-boxed-bit, zero or one.
		Values:
		0	LEFT	Boxed-data bit comes from left source.
		1	RIGHT	Comes from right source.
		2	0	Set to zero.
		3	1	Set to one.
		For Functional-Dest that writes MD or VMA in a way
		that records the boxed bit, the MD bit gets bit 55,
		and the VMA bit gets bit 54.

53..51: DTCHK	Data-type-checking control.  Determines if current ALU
		operation causes a data-type trap.
		Values:
		0..6	Not yet specified.
		7	No trap.

50..48:	CHOP	Call-hardware operation.
		Values:
		0	NOP	  No operation.
		1	OPEN	  Open a new frame.
		2	T-OPEN    Tail-recursive open.
		3	(spare)
		4	CALL	  Activate current open frame and save PC+1.
		5	OPEN-CALL Open and call.
		6	T-CALL    Tail-recursive call.
		7	RETURN	  Return current frame; make old PC available.

47..41:	DEST	Destination address.  Selects register location
		or functional-destination.
		Bit 47 = 0: Register location.  Bits 46..41 select a
			base frame and offset used to form a 12-bit address.
		Bit 47 = 1: Functional destination.  Bits 46..41 select
			one of 64 destinations.

40..37: IMM	Four bit field used as register address bits 7..4 when
		GLOBAL is selected by DEST, LEFT or RIGHT.

36..34:	JCOND	Select jump-condition for next instruction.  Also used as DRET,
		in which case the following instruction must not be a
		conditional jump.
		Values:
		0	JINDIR	Jump condition is JINDIR control-register bit.
		1	TRUE	Unconditional (always specified by default).
		2	C	Jump if carry.
		3	C-	Jump if not-carry.
		4	Z	Jump if zero.
		5	Z-	Jump if not-zero.
		6	C+Z	Jump if carry or zero.
		7	C+Z-	Jump if not (carry or zero).

36..32:	DRET	DRET bits 6..4 for ICAT-ALU, bits 6..2 for ICAT-ADDR.

33..32:	BW	Byte-width bits 1..0 for 29332.

31..25:	RIGHT	Defined for ICAT-ALU and ICAT-ADDR.
		Right-source address.  Bit 31 = 0: bits 30..25 select a
		register; bit 31 = 1: bits 30..25 select functional source.

31..25:	ALUOP	Defined for ICAT-ALUI.
		ALU instruction bits 6..0 for 29332.

24..19:	LEFT	Defined for ICAT-ALU and ICAT-ALUI.
		Left-source register address.  Left-source cannot be
		a functional-source.  If these bits are used by IDATA,
		the register address is meaningless and LEFT must not
		be used by the ALUOP.

24..23:	DRET	DRET bits 1..0 for ICAT-ADDR.

18..12:	ALUOP	Defined for ICAT-ALU.
		ALU instruction bits 6..0 for 29332.

10..5:	SHIFT
4..0:	MASK	Shift bits 5..0 and Mask bits 4..0 for 29332.
		Defined for ICAT-ALU, if ADDR is not used.

3..0:	DRET	DRET bits 3..0 for ICAT-ALU

31..0:	IDATA	32-bit immediate data for ICAT-LOADI.
23..0:	IDATA	24-bit immediate data for ICAT-ALUI.
15..0:	IDATA	16-bit immediate data for ICAT-ALUI.

22..0:	ADDR	23-bit jump address for ICAT-ADDR.
11..0:	ADDR	12-bit jump address within current 4K cluster, for ICAT-ALU.
11..4:	ADDR	12-bit subroutine address within cluster zero, for ICAT-ALU.

;;;;;;;;;;;;;;;;		

Ordered by field name:

ADDR	22..0	23-bit jump address for ICAT-ADDR.
	11..0	12-bit jump address within current 4K cluster, for ICAT-ALU.
	11..4	12-bit subroutine address within cluster zero, for ICAT-ALU.
ALUOP	18..12	for ICAT-ALU
	31..25	2

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