-*- Mode:Text -*- This is Bobp's TO-DO list for the processor hardware ... Four sections: 0. Things to do immediately. 1. Outstanding questions. 2. Caveats and other notes to be remembered. 3. Stuff that isn't important now, but was before and may be again. ================ ================ THINGS TO DO IMMEDIATELY: ;;;; doc. code and clock sequencing for trap entry / exit. fix PC-select logic. OPC on mem board GC / transport logic Enter drawings for: type-checking 8-input boxed-bit mux 24-bit PC ALU macro / link / carry / borrow ================================================================ ================================================================ OUTSTANDING: ;;;; Floating point: Extend instruction decoding to use 3rd ICAT bit. Timing ... ROMS for division. ram address map Specify action of RESET / WARM_BOOT trap? Nubus control reg bits for RESET action: 3 bits: "boot mode". Reset to 0 on RESET. Wait: (0) wait for boot-mode bits to change to non-zero. Test: do self test; report to LEDs and main mem Cold-boot: boot from bands specified in main-mem area Warm-boot: warm boot Dump: dump processor state to main-mem and halt Restore: restore state from main-mem and continue Two connector pins for directly forcing cold-boot and warm-boot. Prom starts running on RESET and loops until boot-mode bits are non-zero. Real-time-clock: source of interrupts at about 60Hz. What is code sequence for Icache flush? Testing Icache: 1. Self-test vs. external debug interface test vs. nubus access 2. how to test tag ram? 3. how to address and write Icache ram while running? Source for Nubus slot-ID on M-board also useful for P-board? ECO register on M-board and P-board 4 bits each what is mechanical form? LEDs on M-board 3 LEDs on edge, writable as Dest. in addition to usual "error" LED? Single-step software trace: What is functionality? Trace-trap bit allows one instruction to execute before it is trapped. What is interaction with other traps? Some traps should run through without trace-traps; perhaps others should be disabled or should trace through? -- trace is highest-pri? change reg-ram addr mux func dest decoding to do: D-GARBAGE = 011110 D-RET = 011111 ALU time for CP to Status is > 50ns Only matters when internal status reg is selected, in trap exit code, but that is asserted for multiple cycles with the clock stopped before it is used, so it shouldn't matter. Parity ... Icache? Easier if Icache is on SIPS? Register ram? Can't depend on ALU parity if using floating-point chip? Software determining clock rate: Software must know exact clock frequency? Matters less with real microsecond clock. Combination of config prom and ECO reg. Boxed-bit: Change to 8-input mux. Normal mode: IR BOX field selects from L / R / 0 / 1. Special mode: IR BOX selects from OUTREG-0 / R / 0 / 1. Control-reg bit selects mode. Output of mux goes to reg-ram data, pass-around and status-reg. ICAT: Was 2 bits: ALU, ALUI, LOADI, ADDR. Now is 3 bits: above, plus ALUX, ALUIX and 2 reserved floating-point instructions New bit provides extra instruction bit for ALU and ALUI; not required for LOADI and ADDR. ALU MACRO input: Comes directly from 3rd ICAT bit (for now). Selects "alternate" ALU instruction space. ALU LINK input: Comes directly from right-side source register (R_IN) boxed-bit. (Not enough time to go through mux.) ALU CARRY input: Wired to 1. ALU BORROW input: Hardwired to what? CALL HARDWARE: Do we need "fake" call / return? Return-then-open etc.? D-return? Indirect register-address path: Requires "RETURN" and one quad 2-input mux, plus 4 bits that can be in a register such as "OPEN". Necessary? Memory-board Traps: Check definition of trap sources GC/Trans, PGF, errors ... Check timing of trap assertions Check priorities of traps Make provision for simple re-ordering of priorities? What state must be saved before recursively enabling traps? Trap-exit: Restarting instruction with ALU input regs frozen may allow machine to source MD even if the data would be ignored. This would be bad if the MD source would cause a trap. Should source-decoding be inhibited during trap exit cycles that inhibit input-reg clocks? Data-type trap must be inhibited as part of the trap-exit sequence: If only the R source clock is disabled, how is the data-type trap inhibited in the re-execution of the aborted instruction? GC / TRANSPORT stuff: 2 bits from DEST go to transport ram. GC-trap only enabled when VMA boxed-bit is set. If memory write causes trap: Trap must occur before MD or VMA are read or written by following instructions. Control / status register: List bits ;;;; DEBUG INTERFACE: Hardware: Only direct control is by forcing instructions to be executed; that is done by driving shifter -> MFIO -> Icache -> IR What signals must go to P-board? What state must be accessible from hardware in order to get the rest by sequencing the machine? Single-step debug clock: Specify capabilities and operation. Only via debug interface. Step one or two C2 cycles? Code sequence for hardware-debug state-save: single-step through trap-entry code for primary state-save; then single-step unrestricted instructions for rest of state. Categories of state-saving: software or nubus-interrupt save-and-halt function dump processor state to main memory; halt software exception hardware interrupt debug-interface non-destructive save (software debug) assuming good hardware debug-interface destructive save (hardware debug) assume minimum good hardware "HALT" What does it mean to "halt" the machine? Ever done as result of software error? As result of hardware error? Halted-state readable from Nubus? -- Stop machine with C2 high after end of C. Next instruction is clocked in IR, but machine is frozen before anything that uses it is clocked, so IR can be changed to force a different instruction to exec next. -- No rams are written during C2 high, so freezing here is OK. ================================================================ ================================================================ CAVEATS: ;;;;;;;;;;;;;;;; Traps: When a trap routine has changed MD to be different than what was put into it because of a VMA-start-read, make sure that successive traps don't accidentally revert MD to being what VMA still points to. This requires that VMA be written without starting a read or otherwise invalidating the data in and trap-state of MD. Interrupts that occur at the same time must be processed and/or remembered; re-executing the aborted instruction may not cause the interrupt again. ;;;;;;;;;;;;;;;; ;Pace's trace-trap info page The trace trap is a feature that can be used to single step a program. It is activated by setting a mode register bit during the trap return sequence. After the trap return, at most one instruction is executed before causing another trap. In other words, the instruction being returned to by the trap is executed normally. If this instruction causes a trap (data type or overflow), or if there is an asynchronous interrupt pending, then that trap will happen, as usual, before the commit point of this instruction. (Notice that the memory system is idle during the return from a trap, so no page-fault or transporter traps can go off.) **bobp: idle yes, but reading MD can still cause a trap. If no traps go off, then a trap is unconditionally signaled at the commit point of the following instruction. ================================================================ ================================================================ OLD INFO: ;;;;;;;;;;;;;;;; Restoring traps vs. interrupts: Interrupts are "easy", because the aborted instruction is re-executed exactly. Traps are hard, because the instruction may or may not be reexecuted, and most likely something will be different. Hardest case may be type-check trap: want to restart same instruction so that it writes a trap-computed dest value using its own dest field, and should inhibit the data-type trap while allowing other types of traps. Note that if source reg clocks are inhibited, the type-checking ram will see what is left in the source regs on trap return, so the trap might be inhibited that way. If it is necessary to return with random values in the sources (not likely) then it is harder. ALU status doesn't matter when returning from trap, but jump status for aborted I does matter. Restore jump-status used by aborted instruction; select it with indir for last I in trap-exit. Don't need to frob internal status reg; jump condition for restarted I is recomputed from new data. ;;;;;;;;;;;;;;;; Ways of handling writes for data cache: 1. Write main mem; flush cache if hit, ignore if miss. Cache miss and reload occurs if read follows. => 2. Write main mem; write cache if hit, ignore if miss. Cache write can't occur until after hit; is slower than read hit. 3. If hit, write cache and indicate delayed write needs to happen; if miss, write to main mem and ignore cache. ;;;;;;;;;;;;;;;; Instruction cache fill / flush: When a PC ref results in an icache hit set Z hit and set Z enabled or set 0 hit and set 0 enabled or set 1 hit and set 1 enabled the cache asserts ICD_VALID, the IR is clocked with ICD on the next C, and the processor clocks are left enabled. If the PC ref did not result in a hit, ICD_VALID is deasserted before C, inhibiting all processor clocks until valid data is present on ICD and ICD_VALID is asserted before a C. The cache then does one of the following: no sets enabled (single word goes through cache): do one double-word memory cycle, write 64-bits to appropriate set Z location, enable and select set Z output, assert ICD_VALID all sets enabled, flush disabled: select and reset fillpc counter start 8-word-burst ram read. if set Z addr, write into set Z and set tag valid bit. else, select (random) set 0 or 1, write, and set tag valid bit. one of set 0 or set 1; set Z or not set Z: same as above, but without random select. set 0 and set 1 disabled; set Z enabled: if set Z addr, do normal set Z fill; else do one double-word mem cycle and reset tag valid. this would be easier if the IR could be loaded without going through the cache ram. can drive MFI through MD? cache-bypass: L_MD -> MFI -> MFIO -> ICD (too much trouble to do both ways) prom: SHIFTER -> MFIO -> ICD? both prom and IC must drive ICD_VALID? what about loading cache through L_MD -> MFI -> MFIO -> ICD? (too slow) how to fill set Z: 1. active edge of set Z enable causes 4K burst of ram reads. 2. valid bit for each block of set Z; use same fill process as for set0/1. ;;;;;;;;;;;;;;;; CONS hardware assist: Required? On M-board ... ;;;;;;;;;;;;;;;;