From root Wed Jan 29 17:57:39 MEZ 1986 >From hpfloat!bayes Wed Jan 29 17:57:30 1986 remote from hpfcla Return-Path: <@hpfcla.UUCP:bayes@hpfloat> Received: by hpbbn.UUCP (5.4/30-Jul-85) id AA26641; Wed, 29 Jan 86 17:50:47 mez Date: Wed, 29 Jan 86 17:50:47 mez From: hpfcla!hpfloat!bayes To: hpfcla!jws Status: R John, here are 2 mail messages from Rick Greer and Bruce Bergmann, describing the Bobcat-32 DMA design. The first point they state being that the card has a (default) 98620B compatibility mode, we may just be able to lie back and enjoy this one. I'll attend the meeting, so if you want anything said there, it would be best to mail me ASAP with the Word. Scott ========================================================================= >From uucp Tue Jan 28 16:15:08 1986 >From uucp Tue Jan 28 16:03:18 1986 remote from hpfcla >From rick Tue Jan 28 16:01:51 1986 remote from hpfclm To: bruce, byron, dahms, dan, hpfcla!bayes, hpfcla!febvre, hpfcla!jpc, hpfcla!russ, hpfcla!steve, hpfcla!stevej, hpfcla!twc, nick, rick, ron Subject: DMA chip features alert Status: R For the BOBCAT-32 program, we plan to replace the 98620B DMA board with a semi-custom IC. We plan to add extensions to the 98620B definition in order to support 32 bit address and data busses. This DMA chip will be integrated onto the BOBCAT32 processor boards. To meet project schedule, we need to resolve any issues and freeze the design as soon as possible. The 98620B compatibile features and extensions we plan to implement are: 98620B compatible mode Two (2) channels Five (5) hardware interrupt Levels Daisy chain bus arbitration * Extended transfer size * Block mode protocol * 32-bit physical address * Byte, word, word.l transfers * 12.5 MHZ clock * Programmable bus bandwidth utilization * Re-run mode (for disc buffer operations) * = Signifies extensions Other features which we have investigated, but currently do not plan to implement are: *) Memory init mode *) Memory-to-memory DMA *) Chaining DMA Details of these features will be forwarded to you following this notice. We would appreciated your comments on the intended feature set, any concerns, issues or suggestions you may have. We would like to have a (hopefully) brief meeting to resolve any issues and freeze the design; please invite anyone who might be able to provide constuctive input: Time: 3:00 p.m. Date: Thursday, 30 Jan 86 Place: 1UT10B Objectives: A1) Freeze the design a) Clear up any misconceptions regarding the core set. b) Re-visit the need, if any, for the investigated, but not planned, features. By Friday, 31 Jan 86, we hope to close the matter of features to be implemented. If you have any concerns, now is the time to please let us know. Under separate mail, we are sending each of you a brief architectural document on the incremental features. Thanks for your attention to this matter. Regards, Rick Greer (hpfcla!rick-g) x2610 Bruce Bergmann (hpfcla!bruce) x3978 >From uucp Wed Jan 29 08:25:06 1986 >From uucp Wed Jan 29 08:15:26 1986 remote from hpfcla >From rick Wed Jan 29 08:14:02 1986 remote from hpfclm To: bruce, byron, dahms, dan, hpfcla!bayes, hpfcla!febvre, hpfcla!jpc, hpfcla!rick-g, hpfcla!russ, hpfcla!steve, hpfcla!stevej, hpfcla!twc, nick, ron Subject: DMA chip architecture Status: R As promised in our previous posting, here is the short architecture document on the DMA chip planned incremental features. Regards, - Bruce Bergmann (hpfcla!bruce) x3978 - Rick Greer (hpfcla!rick-g) x2610 <*><*><*><*> D O C U M E N T F O L L O W S <*><*><*><*> III. DMA CHIP REGISTER DEFINITIONS 98620B REGISTERS: ---------------- The DMA chip provides the complete 98620B interface for backwards compatibility, but has a full 32-bit physical address range in order to support both the DIO and DIO-II buses. The definitions of these registers are identical to that of the 98620B. To be expedient, these definitions won't be discussed here today. Come see Bruce Bergmann or Rick Greer if you need further detail. 98620C REGISTERS: ---------------- MEMORY MAP "98620C" General control register base address: 00500010 (hex) 98620C ID and GENERAL STATUS/CONTROL ------------------------------------ OFF ADDR R/W NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R ID << UPPER WORD OF PRODUCT NUMBER ID >> 2 R ID << LOWER WORD OF PRODUCT NUMBER ID >> 4 R ID << ENGR RESP DIV >> << MASK REVISION >> 6 R ID <<< D A T E C O D E >>> 8 R/W GEN CONTROL T xx xx xx xx xx xx xx xx xx R R < BT> < BR> E E E S S S T E E T T 1 0 A R/W TEST xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx COMMAND <<<< undefined >>>> 98620C CHANNEL SPECIFIC REGISTERS --------------------------------- "98620C" Channel 0 control register base address: 00500100 (hex) "98620C" Channel 1 control register base address: 00500200 (hex) OFF ADDR R/W NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 00 R/W Primary A A A A A A A A A A A A A A A A address, 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 high word 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 02 R/W Primary A A A A A A A A A A A A A A A A address, 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 low word 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 04 R/W Transfer C C C C C C C C C C C C C C C C count, 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 high word 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 06 R/W Transfer C C C C C C C C C C C C C C C C count, 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 low word 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 08 R/W CONTROL S R X X X < BLK > X P O W I T E X X X < SIZ > X < LEVEL> R / / N A R X X X X < 7:3 > I I' B' T R U X X X X T N X X X X 0A R STATUS xx xx xx xx xx xx xx xx xx xx xx xx I A xx xx xx xx xx xx xx xx xx xx xx xx N R xx xx xx xx xx xx xx xx xx xx xx xx T M xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx 98620C REGISTER FUNCTION DESCRIPTIONS 98620C REGISTERS: ---------------- The DMA chip provides the complete 98620C interface to support both the DIO and DIO-II bus. The 98620C architecture isn't compatible with the 98620B, but provides the following additional features: 1) Read/write control and status registers, 2) Restart capability. 3) Re-run capability for writing to buffers. *** 4) DIO-II block transfers of up to 64 word.l per block. 5) Programmable priority wait time. 6) Programmable bus utilization percentage. The 98620C contains general registers and channel specific registers. The addresses of these registers are: 98620C general regs: $00500010 (hex) 98620C channel 0 regs: $00500100 (hex) 98620C channel 1 regs: $00500200 (hex) The 98620C general register definitions are: 98620C ID (read register $0,$4) The register is actually two long words which identify the chip. The long word at offset $0, is the ASCII encoded product number of the chip. (( it should read 98620C )). The long word at offset $4 contains three ASCII encoded fields. Field definition Location --------------------------------- ----------------------------- Engineering Responsible Division high byte of high word Chip mask revision low byte of high word Engineering Date Code low word 98620C GENERAL CONTROL (read/write reg $8, byte operations allowed) This register contains five valid fields. These are BR (bit 1:0): Bandwidth Restriction. These bits set the upper limit for the amount of DIO-II bus bandwidth that the DMA chip is allowed to have. The restriction is defined according to the following table: bit 1:0 bandwidth limit (%) ------- ------------------- 0 0 100 0 1 50 1 0 25 1 1 12.5 BT (bit 3:2): Burst Wait Time. These bits set the upper limit for the time that the DMA chip will wait for a I/O card to request a DMA transfer when the priority bit is set for the channel. The restriction is defined according to the following table: bit 3:2 burst time (clocks) ------- --------------- 0 0 4 0 1 8 1 0 16 1 1 32 RESET0 (bit 4): When set (high), 98620C DMA channel 0 is reset. The chip automatically clears this bit upon completion of the reset. Resetting the channel does not effect the primary address register (PAR) or transfer count register (TCR). However, the channel will restore to the following defaults: 1) Buffer register is cleared. ($00000000) 2) Status register is cleared. ($0000) 3) Control register is cleared. ($0000) 4) General control register bit 15 is cleared. 5) Bandwidth restriction is set 100%. 6) Burst time is set to 4 clocks. RESET1 (bit 5): Setting this bit has the same effect as setting RESET0 except the reset is performed on channel 1 instead of channel 0. TEST (bit 15): Setting this bit causes the chip to enter test mode. TEST COMMAND (read/write register $A) The bits and functions of this register is not defined, and may be dropped from the definition. This register is valid only when the test bit is set in the general control register. 98620C CHANNEL SPECIFIC REGISTERS --------------------------------- "98620C" Channel 0 control register base address: 00500100 (hex) "98620C" Channel 1 control register base address: 00500200 (hex) PRIMARY ADDRESS REGISTER (r/w reg $00 & $02, byte operations NOT allowed) The PRIMARY ADDRESS REGISTER is a 32-bit read/write register that increments and holds the DMA memory address pointer. The address register can be loaded with one move long word (MOVE.L) instruction, since the high and low words of the address are in sequence. BYTE operations are not allowed. TRANSFER COUNT REGISTER (r/w reg $04 & $06, byte operations NOT allowed) The TRANSFER COUNT REGISTER is a 32-bit read/write register that holds and decrements the current remaining number of bytes to be transferred minus 1. The register is decremented once for each byte, twice for each word and four times for each long word transferred. Since the register is 32-bits wide, this permits continuous transfers of up to 4G bytes. CHANNEL CONTROL REGISTER (read/write reg $08, byte operations allowed) INT (bit 0): Same definition as 98620B. W/B' (bit 1): Same definition as 98620B. O/I' (bit 2): Same definition as 98620B. PRI (bit 3): Same definition as 98620B. INT LEVEL: (bits 6:4) Same definition as 98620B. BLKSIZ (b 10:8): BLKSIZ is a three bit field which defines the block size of a block transfer. The DMA chip can coordinate block transfers of up to 64 long words (256 bytes) per transfer. If the block size is 0 then the transfer type will be a byte or word transfer. Values for BLKSIZ are: Bit # word.l bytes 10 9 8 tfr/blk tfr/blk --- --- --- ------- ------- 0 0 0 0 1,2 (default) 0 0 1 1 4 0 1 0 4 16 0 1 1 8 32 1 0 0 16 64 1 0 1 32 128 1 1 0 64 256 Note: There exists a restriction in the DIO-II bus which states that no block transfers can cross a 256 byte boundry. The purpose of this restriction is to minimize imple- mentation impact on slave devices. The DMA chip honors this restriction. When a 256 byte boundry is encountered, the DMA chip will halt the block transfer and restrobe a new address. System software should take this into con- sideration when setting up the buffers. RERUN (bit 14): Setting this bit causes the primary address register (PAR) and transfer count register (TC) to be initialized to the value of backup registers when the channel is started. The PAR or TC main registers each has backup registers. The backup registers capture the data which is written to the main registers. This action is invisible to the operating system. The backup registers download their data to the main registers if the RERUN bit is set when the channel is armed. DMA can then begin. START (bit 15): START. Writing a 1 to this bit does not actually set the START bit. Instead, the status register arm bit is set and the channel is armed; and the error codes in the channel status register are cleared. The powerup and reset state of both channel control registers is: CONTROL LINE DEFAULT EFFECT ------------ ------- ----------------------------------------- INT (b0) 0 do not interrupt on done or error W/B' (b1) 0 byte transfers O/I' (b2) 0 dma direction is IN PRI (b3) 0 channel priority is 0 (lowest) INT LVL (b6:4) $0 channel interrupt level is 3 xxxxx (b7) x << not implemented >> BLKSIZ (b10:8) $0 transfer size is partial (byte or word) xxxxx (b11) x << not implemented >> xxxxx (b12) x << not implememted >> xxxxx (b13) x << not implemented >> RERUN (b14) 0 don't load PAR and TC regs from backup START (b15) 0 do not arm DMA channel CHANNEL STATUS REGISTER (read reg $0A, byte operations allowed) ARM (bit 0): If set, indicates that the channel is enabled to do DMA transfers. Any of four conditions will clear the ARM bit: 1) Normal DMA termination. 2) Bus error termination. 3) General system hardware reset. 4) Software-controlled reset. INT (bit 1): If set, indicates that the DMA interface is inter- rupting on a level determined by bits 4-6 of the channel control register. INT can only be set if all of the following conditions are true: 1) Bit 0 (interrupt control) is already set in the CONTROL register; and 2) A normal or error termination occurs. The only way to reset the INT bit is to reset the channel. Note that since the DMA channels are independent, clearing the interrupt bit for one channel has no effect upon that status of the other channel. ERRCODE (b 3:2): ERROR CODE. Error status is defined by these two bits as follows: bit 3:2 error condition ------- ----------------------------- 0 0 no error 0 1 operation timing error 1 0 software halt 1 1 bus error An OPERATION TIMING ERROR occurs when any of the channel control register, other than START or RERUN bits, is changed before normal channel termination. A SOFTWARE HALT ERROR occurs when the OS halts the channel by setting the appropriate RESETx' bits in the general control register. A BUS ERROR occurs when the DMA chip BERR' input is asserted by the chip host. It normally indicates that a timeout condition on BAS has occurred.