.TOC "MACRO.MIC -- Macro Definitions" .TOC "Revision 2.0" ; Bob Supnik .nobin ;**************************************************************************** ;* * ;* COPYRIGHT (c) 1988, 1989 BY * ;* DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASSACHUSETTS. * ;* ALL RIGHTS RESERVED. * ;* * ;* THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY BE USED AND COPIED * ;* ONLY IN ACCORDANCE WITH THE TERMS OF SUCH LICENSE AND WITH THE * ;* INCLUSION OF THE ABOVE COPYRIGHT NOTICE. THIS SOFTWARE OR ANY OTHER * ;* COPIES THEREOF MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY * ;* OTHER PERSON. NO TITLE TO AND OWNERSHIP OF THE SOFTWARE IS HEREBY * ;* TRANSFERRED. * ;* * ;* THE INFORMATION IN THIS SOFTWARE IS SUBJECT TO CHANGE WITHOUT NOTICE * ;* AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL EQUIPMENT * ;* CORPORATION. * ;* * ;* DIGITAL ASSUMES NO RESPONSIBILITY FOR THE USE OR RELIABILITY OF ITS * ;* SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL. * ;* * ;**************************************************************************** .TOC " Revision History" ; Edit Date Who Description ; ---- --------- --- --------------------- ; (2)0 15-Nov-89 RMS Revised for simplified decoder. ; 6 06-Nov-89 RMS Added LAST CYCLE IF LONG macro. ; 5 25-Sep-89 RMS Added IntWBUS ZEXT shift macro. ; 4 14-Aug-89 RMS Revised SEXT macro. ; 3 07-Jul-89 RMS Revised RESTORE from RLOG macro. ; 2 22-Jun-89 RMS Revised CONSOLE HALT macro for initialization. ; 1 21-Jun-89 RMS Revised, added macros for initialization. ; (1)0 11-Jun-89 RMS Revised right shifts and for release to CMS. ; 5 24-May-89 RMS Added new functions. ; 4 18-Apr-89 RMS Revised RLOG pop macro. ; 3 07-Apr-89 RMS Removed SELECT from decoder next macros. ; 2 01-Feb-89 RMS Revised for new microbranch latencies. ; 1 10-Jan-89 RMS Revised for new microarchitecture. ; (0)0 14-Oct-88 RMS First edit for Raven. .TOC " ADR Macros" ; ADR macros with register operands. VA <-- [] + [] "LIT/BREG,ADR/A.PLUS.B,A/@1,B/@2" VA <-- [] - [] "LIT/BREG,ADR/A.MINUS.B,A/@1,B/@2" VA <-- [] "ADR/PASS.A,A/@1" VA <-- B [] "LIT/BREG,ADR/PASS.B,B/@1" VA <-- [] + 4 "ADR/A.PLUS.4,A/@1" VA <-- [] - 4 "ADR/A.MINUS.4,A/@1" ; ADR macros with constant operand. VA <-- [] + 000000[] "LIT/LIT,POS/BYTE0,ADR/A.PLUS.B,CONST/@2,A/@1" VA <-- [] - 000000[] "LIT/LIT,POS/BYTE0,ADR/A.MINUS.B,CONST/@2,A/@1" VA <-- 000000[] "LIT/LIT,POS/BYTE0,ADR/PASS.B,CONST/@1" VA <-- [] + 0000[]00 "LIT/LIT,POS/BYTE1,ADR/A.PLUS.B,CONST/@2,A/@1" VA <-- [] - 0000[]00 "LIT/LIT,POS/BYTE1,ADR/A.MINUS.B,CONST/@2,A/@1" VA <-- 0000[]00 "LIT/LIT,POS/BYTE1,ADR/PASS.B,CONST/@1" VA <-- [] + 00[]0000 "LIT/LIT,POS/BYTE2,ADR/A.PLUS.B,CONST/@2,A/@1" VA <-- [] - 00[]0000 "LIT/LIT,POS/BYTE2,ADR/A.MINUS.B,CONST/@2,A/@1" VA <-- 00[]0000 "LIT/LIT,POS/BYTE2,ADR/PASS.B,CONST/@1" VA <-- [] + []000000 "LIT/LIT,POS/BYTE3,ADR/A.PLUS.B,CONST/@2,A/@1" VA <-- [] - []000000 "LIT/LIT,POS/BYTE3,ADR/A.MINUS.B,CONST/@2,A/@1" VA <-- []000000 "LIT/LIT,POS/BYTE3,ADR/PASS.B,CONST/@1" .TOC " ALU Macros" ; ALU macros with register operands. [] <-- [] + [] "LIT/BREG,ALU.SHF/A.PLUS.B,DST/@1,A/@2,B/@3" [] <-- [] + [] + 1 "LIT/BREG,ALU.SHF/A.PLUS.B.PLUS.1,DST/@1,A/@2,B/@3" [] <-- [] - [] "LIT/BREG,ALU.SHF/A.MINUS.B,DST/@1,A/@2,B/@3" [] <-- [] - [] - 1 "LIT/BREG,ALU.SHF/A.MINUS.B.MINUS.1,DST/@1,A/@2,B/@3" [] <-- [] + NOT [] "LIT/BREG,ALU.SHF/A.MINUS.B.MINUS.1,DST/@1,A/@2,B/@3" [] <-- [] AND [] "LIT/BREG,ALU.SHF/A.AND.B,DST/@1,A/@2,B/@3" [] <-- [] ANDNOT [] "LIT/BREG,ALU.SHF/A.AND.NOT.B,DST/@1,A/@2,B/@3" [] <-- [] OR [] "LIT/BREG,ALU.SHF/A.OR.B,DST/@1,A/@2,B/@3" [] <-- [] XOR [] "LIT/BREG,ALU.SHF/A.XOR.B,DST/@1,A/@2,B/@3" [] <-- (-[] + []) "LIT/BREG,ALU.SHF/B.MINUS.A,DST/@1,A/@2,B/@3" [] <-- [] "ALU.SHF/PASS.A,DST/@1,A/@2" [] <-- ZEXTW [] "ALU.SHF/ZEXTW.A,DST/@1,A/@2" [] <-- B [] "LIT/BREG,ALU.SHF/PASS.B,DST/@1,B/@2" [] <-- -B [] "LIT/BREG,ALU.SHF/NEG.B,DST/@1,B/@2" ; ALU macros, continued. ; ALU macros with constant operand. [] <-- [] + 000000[] "LIT/LIT,POS/BYTE0,ALU.SHF/A.PLUS.B,CONST/@3,DST/@1,A/@2" [] <-- [] - 000000[] "LIT/LIT,POS/BYTE0,ALU.SHF/A.MINUS.B,CONST/@3,DST/@1,A/@2" [] <-- 000000[] - [] "LIT/LIT,POS/BYTE0,ALU.SHF/B.MINUS.A,CONST/@2,DST/@1,A/@3" [] <-- [] AND 000000[] "LIT/LIT,POS/BYTE0,ALU.SHF/A.AND.B,CONST/@3,DST/@1,A/@2" [] <-- [] OR 000000[] "LIT/LIT,POS/BYTE0,ALU.SHF/A.OR.B,CONST/@3,DST/@1,A/@2" [] <-- [] ANDNOT 000000[] "LIT/LIT,POS/BYTE0,ALU.SHF/A.AND.NOT.B,CONST/@3,DST/@1,A/@2" [] <-- [] XOR 000000[] "LIT/LIT,POS/BYTE0,ALU.SHF/A.XOR.B,CONST/@3,DST/@1,A/@2" [] <-- 000000[] "LIT/LIT,POS/BYTE0,ALU.SHF/PASS.B,CONST/@2,DST/@1" [] <-- [] + 0000[]00 "LIT/LIT,POS/BYTE1,ALU.SHF/A.PLUS.B,CONST/@3,DST/@1,A/@2" [] <-- [] - 0000[]00 "LIT/LIT,POS/BYTE1,ALU.SHF/A.MINUS.B,CONST/@3,DST/@1,A/@2" [] <-- 0000[]00 - [] "LIT/LIT,POS/BYTE1,ALU.SHF/B.MINUS.A,CONST/@2,DST/@1,A/@3" [] <-- [] AND 0000[]00 "LIT/LIT,POS/BYTE1,ALU.SHF/A.AND.B,CONST/@3,DST/@1,A/@2" [] <-- [] OR 0000[]00 "LIT/LIT,POS/BYTE1,ALU.SHF/A.OR.B,CONST/@3,DST/@1,A/@2" [] <-- [] ANDNOT 0000[]00 "LIT/LIT,POS/BYTE1,ALU.SHF/A.AND.NOT.B,CONST/@3,DST/@1,A/@2" [] <-- [] XOR 0000[]00 "LIT/LIT,POS/BYTE1,ALU.SHF/A.XOR.B,CONST/@3,DST/@1,A/@2" [] <-- 0000[]00 "LIT/LIT,POS/BYTE1,ALU.SHF/PASS.B,CONST/@2,DST/@1" [] <-- [] + 00[]0000 "LIT/LIT,POS/BYTE2,ALU.SHF/A.PLUS.B,CONST/@3,DST/@1,A/@2" [] <-- [] - 00[]0000 "LIT/LIT,POS/BYTE2,ALU.SHF/A.MINUS.B,CONST/@3,DST/@1,A/@2" [] <-- 00[]0000 - [] "LIT/LIT,POS/BYTE2,ALU.SHF/B.MINUS.A,CONST/@2,DST/@1,A/@3" [] <-- [] AND 00[]0000 "LIT/LIT,POS/BYTE2,ALU.SHF/A.AND.B,CONST/@3,DST/@1,A/@2" [] <-- [] OR 00[]0000 "LIT/LIT,POS/BYTE2,ALU.SHF/A.OR.B,CONST/@3,DST/@1,A/@2" [] <-- [] ANDNOT 00[]0000 "LIT/LIT,POS/BYTE2,ALU.SHF/A.AND.NOT.B,CONST/@3,DST/@1,A/@2" [] <-- [] XOR 00[]0000 "LIT/LIT,POS/BYTE2,ALU.SHF/A.XOR.B,CONST/@3,DST/@1,A/@2" [] <-- 00[]0000 "LIT/LIT,POS/BYTE2,ALU.SHF/PASS.B,CONST/@2,DST/@1" [] <-- [] + []000000 "LIT/LIT,POS/BYTE3,ALU.SHF/A.PLUS.B,CONST/@3,DST/@1,A/@2" [] <-- [] - []000000 "LIT/LIT,POS/BYTE3,ALU.SHF/A.MINUS.B,CONST/@3,DST/@1,A/@2" [] <-- []000000 - [] "LIT/LIT,POS/BYTE3,ALU.SHF/B.MINUS.A,CONST/@2,DST/@1,A/@3" [] <-- [] AND []000000 "LIT/LIT,POS/BYTE3,ALU.SHF/A.AND.B,CONST/@3,DST/@1,A/@2" [] <-- [] OR []000000 "LIT/LIT,POS/BYTE3,ALU.SHF/A.OR.B,CONST/@3,DST/@1,A/@2" [] <-- [] ANDNOT []000000 "LIT/LIT,POS/BYTE3,ALU.SHF/A.AND.NOT.B,CONST/@3,DST/@1,A/@2" [] <-- [] XOR []000000 "LIT/LIT,POS/BYTE3,ALU.SHF/A.XOR.B,CONST/@3,DST/@1,A/@2" [] <-- []000000 "LIT/LIT,POS/BYTE3,ALU.SHF/PASS.B,CONST/@2,DST/@1" ; Special ALU macros. NOP "[WBUS] <-- 000000[00],LONG" SET PSL(V) "[WBUS] <-- 000000[01],LONG,SET PSL CC (PPJP)" CLEAR PSL(V) "[WBUS] <-- 000000[00],LONG,SET PSL CC (PPJP)" [] <-- CTRL FLAGS "ALU.SHF/CTRL.FLAGS,DST/@1" [] <-- ERROR REG "ALU.SHF/ERROR.REG,DST/@1" [] <-- FPU RESULT 1 "ALU.SHF/FPU.RESULT.1,DST/@1" [] <-- FPU RESULT 2 "ALU.SHF/FPU.RESULT.2,DST/@1" .TOC " SHIFT Macros" [] <-- [] LROT [] "LIT/BREG,VAL/@3,DST/@1,A/@2,B/@2,ALU.SHF/LEFT.VAL" [] <-- [] LROT (SC) "LIT/BREG,DST/@1,A/@2,B/@2,ALU.SHF/LEFT.SC" [] <-- [] LROT (VA) "LIT/BREG,DST/@1,A/@2,B/@2,ALU.SHF/LEFT.VA" [] <-- [] RROT [] "LIT/BREG,VAL/<.DIFF[32.,@3]>,DST/@1,A/@2,B/@2,ALU.SHF/LEFT.VAL" [] <-- [] RROT (VA) "LIT/BREG,DST/@1,A/@2,B/@2,ALU.SHF/LEFT.32-VA" [] <-- []!![] LSH [] "LIT/BREG,VAL/@4,DST/@1,A/@2,B/@3,ALU.SHF/LEFT.VAL" [] <-- []!![] LSH (SC) "LIT/BREG,DST/@1,A/@2,B/@3,ALU.SHF/LEFT.SC" [] <-- []!![] LSH (SC 1-32) "LIT/BREG,DST/@1,A/@2,B/@3,ALU.SHF/LEFT.SC.1-32" [] <-- []!![] LSH (VA) "LIT/BREG,DST/@1,A/@2,B/@3,ALU.SHF/LEFT.VA" [] <-- []!![] RSH [] "LIT/BREG,VAL/<.DIFF[32.,@4]>,DST/@1,A/@2,B/@3,ALU.SHF/LEFT.VAL" [] <-- []!![] RSH (VA) "LIT/BREG,DST/@1,A/@2,B/@3,ALU.SHF/LEFT.32-VA" [] <-- [] LSH [] "LIT/BREG,VAL/@3,DST/@1,A/@2,B/K0,ALU.SHF/LEFT.VAL" [] <-- [] LSH (SC) "LIT/BREG,DST/@1,A/@2,B/K0,ALU.SHF/LEFT.SC" [] <-- [] LSH (DL) "LIT/BREG,DST/@1,A/@2,B/K0,ALU.SHF/LEFT.DL" [] <-- SEXT [] "LIT/BREG,VAL/0,DST/@1,A/SEXT.B,B/@2,ALU.SHF/LEFT.VAL" [] <-- SEXT [] LSH (SC) "LIT/BREG,DST/@1,A/SEXT.B,B/@2,ALU.SHF/LEFT.SC" [] <-- SEXT [] LSH (SC 1-32) "LIT/BREG,DST/@1,A/SEXT.B,B/@2,ALU.SHF/LEFT.SC.1-32" [] <-- SEXT [] RSH [] "LIT/BREG,VAL/<.DIFF[32.,@3]>,DST/@1,A/SEXT.B,B/@2,ALU.SHF/LEFT.VAL" [] <-- ZEXT [] LSH (SC) "LIT/BREG,DST/@1,A/K0,B/@2,ALU.SHF/LEFT.SC" [] <-- ZEXT [] LSH (SC 1-32) "LIT/BREG,DST/@1,A/K0,B/@2,ALU.SHF/LEFT.SC.1-32" [] <-- ZEXT [] RSH [] "LIT/BREG,VAL/<.DIFF[32.,@3]>,DST/@1,A/K0,B/@2,ALU.SHF/LEFT.VAL" ; Special ALU and SHIFT macros for IntWBUS. ; The Intermediate Wbus (IntWBUS) is the portion of the Wbus between the ALU/shifter multiplexor ; and the Wbus source multiplexor. Microbranch conditions, SC input, PSL input, etc are taken ; from IntWBUS rather than WBUS proper. This allows for certain operations, such as microtests, ; SC loads, PSL loads, etc, to take place underneath reads. ; Because IntWBUS operations are rare, only the macros necessary for the microcode have been defined. IntWBUS <-- [] "ALU.SHF/PASS.A,A/@1" IntWBUS <-- B [] "LIT/BREG,ALU.SHF/PASS.B,B/@1" IntWBUS <-- [] XOR [] "LIT/BREG,ALU.SHF/A.XOR.B,A/@1,B/@2" IntWBUS <-- 000000[] "LIT/LIT,POS/BYTE0,ALU.SHF/PASS.B,CONST/@1" IntWBUS <-- [] AND 000000[] "LIT/LIT,POS/BYTE0,ALU.SHF/A.AND.B,CONST/@2,A/@1" IntWBUS <-- [] AND 00[]0000 "LIT/LIT,POS/BYTE2,ALU.SHF/A.AND.B,CONST/@2,A/@1" IntWBUS <-- []!![] LSH [] "LIT/BREG,VAL/@3,A/@1,B/@2,ALU.SHF/LEFT.VAL" IntWBUS <-- []!![] RSH [] "LIT/BREG,VAL/<.DIFF[32.,@3]>,A/@1,B/@2,ALU.SHF/LEFT.VAL" IntWBUS <-- ZEXT [] RSH [] "LIT/BREG,VAL/<.DIFF[32.,@2]>,A/K0,B/@1,ALU.SHF/LEFT.VAL" .TOC " CREQ Macros" [] <-- MEM (VA) "CRQ/READ.V.RCHK,DST/@1" [] <-- MEM.AT (VA) "CRQ/READ.V.ATCHK,DST/@1" [] <-- MEM.LOCK (VA) "CRQ/READ.LOCK.V.WCHK,DST/@1" [] <-- MEM.MOD (VA) "CRQ/READ.MOD.V.WCHK,DST/@1" [] <-- MEM.NOCHK (VA) "CRQ/READ.V.NOCHK,DST/@1" [] <-- MEM.PHYS (VA) "CRQ/READ.P.NOCHK,DST/@1" [] <-- MEM.PPTE (VA) "CRQ/READ.V.PPTE,DST/@1" [] <-- MEM.SPTE (VA) "CRQ/READ.P.SPTE,DST/@1" [] <-- MEM.WCHK (VA) "CRQ/READ.V.WCHK,DST/@1" MEM (VA)& "CRQ/WRITE.V.WCHK" MEM.NOCHK (VA)& "CRQ/WRITE.V.NOCHK" MEM.PHYS (VA)& "CRQ/WRITE.P.NOCHK" MEM.PPTE (VA)& "CRQ/WRITE.V.PPTE" MEM.SPTE (VA)& "CRQ/WRITE.P.SPTE" MEM.UNLOCK (VA)& "CRQ/WRITE.UNLOCK.V.WCHK" [] <-- RESTART CACHE REQUEST "CRQ/CRQ.RESTART,DST/@1,LIT/BREG,B/WDR,ALU.SHF/PASS.B" [] <-- RESTART CACHE REQUEST ALIGNED "CRQ/CRQ.RESTART.ALIGN,DST/@1,LIT/BREG,B/WDR,ALU.SHF/PASS.B" PROBE READ (VA) "CRQ/PROBE.V.RCHK" PROBE WRITE (VA) "CRQ/PROBE.V.WCHK" NEW PC "CRQ/LOAD.PC" NEW PC IF BCOND "CRQ/COND.LOAD.PC" NEW PIBA "CRQ/LOAD.PIBA" RESYNC FROM TRAP "CRQ/FLUSH.IB" CLEAR LOCK "CRQ/CLEAR.LOCK" FLUSH WRITE BUFFERS "CRQ/FLUSH.WRITE.BUFFERS" WRITE CACHE BLOCK "CRQ/WRITE.BLOCK.P.NOCHK" NEW MAPEN AND STATUS "CRQ/LOAD.MAPEN.STATUS" TB WRITE "CRQ/TB.WRITE" TB INVALIDATE "CRQ/TB.INVAL" PCACHE WRITE "CRQ/PCACHE.WRITE" PCACHE INVALIDATE "CRQ/PCACHE.INVAL" .TOC " RS, LEN, MISC Field Macros" SET NORETRY "RS/SET.NO.RETRY" BYTE "LEN/BYTE" WORD "LEN/WORD" LONG "LEN/LONG" LEN(DL) "LEN/LEN(DL)" SC& "MISC/WRITE.SC" NEW PSW "MISC/WRITE.PSW" NEW PSL "MISC/WRITE.PSL" NEW CTRL FLAGS "MISC/WRITE.CTRL.FLAGS" RLOG "MISC/RLOG" PC <-- BACKUP PC "MISC/RESTORE.PC" STATE.0 <-- 1 "MISC/SET.STATE.0" STATE.1 <-- 1 "MISC/SET.STATE.1" STATE.2 <-- 1 "MISC/SET.STATE.2" STATE.3 <-- 1 "MISC/SET.STATE.3" STATE.4 <-- 1 "MISC/SET.STATE.4" STATE.5 <-- 1 "MISC/SET.STATE.5" STATE.3-0 <-- 0 "MISC/CLR.STATE.3-0" STATE.5-4 <-- 0 "MISC/CLR.STATE.5-4" ENABLE TRAPS "MISC/ENABLE.TRAPS" XMIT FPU LW (ENABLE) "MISC/XMIT.FPU.LW.ENABLE" DISABLE TRAPS "MISC/DISABLE.TRAPS" SET PSL CC (IIIP) "MISC/SET.PSL.CC.IIIP" SET PSL CC (IIIP.QUAD) "MISC/SET.PSL.CC.IIIP.QUAD" SET PSL CC (JIZJ) "MISC/SET.PSL.CC.JIZJ" SET PSL CC (IIII) "MISC/SET.PSL.CC.IIII" SET PSL CC (IIIJ) "MISC/SET.PSL.CC.IIIJ" SET PSL CC (PPJP) "MISC/SET.PSL.CC.PPJP" RESTORE REG FROM RLOG "[R0] <-- [R0] + [KDL],LONG,MISC/READ.RLOG" .TOC " Microsequencer Macros" GOTO [] "OR/NO,MUX/GOTO,NA/@1" CALL [] "OR/NO,MUX/CALL,NA/@1" CASE AT [] "OR/YES,MUX/GOTO,NA/@1" CALL CASE AT [] "OR/YES,MUX/CALL,NA/@1" EXIT TRAP "OR/NO,MUX/TRAP.SILO,NA/0,SELECT [TP.Z.DL]" RETURN "OR/NO,MUX/STACK,NA/0" DECODE NEXT IF LONG "MUX/DEC.NEXT.L,SELECT [TP.Z.DL]" DECODE NEXT IF BWL "MUX/DEC.NEXT.BWL,SELECT [TP.Z.DL]" DECODE NEXT "OR/NO,MUX/DEC.NEXT,NA/0,SELECT [TP.Z.DL]" LAST CYCLE "OR/NO,MUX/LAST.CYCLE,NA/0,SELECT [TP.Z.DL]" LAST CYCLE ENABLE OVERFLOW "OR/NO,MUX/LAST.CYCLE.OVERFLOW,NA/0,SELECT [TP.Z.DL]" ELSE [] "OR/NO,NA/@1" ELSE CASE AT [] "OR/YES,NA/@1" SELECT [] "FMT/BRANCH,BCS.1/@1" .TOC " Error Macros" ; These macros provide standard entries to microcode error routines. CONSOLE HALT [] "[W6] <-- 0000[@1]00,LONG,FLUSH WRITE BUFFERS,SET NORETRY,GOTO [CONSOLE.HALT]" MACHINE CHECK [] "[W3] <-- 000000[@1],LONG,FLUSH WRITE BUFFERS,GOTO [IE.MACHINE.CHECK]" RESERVED OPERAND FAULT "GOTO [IE.RSRV.OPERAND]" RESERVED INSTRUCTION FAULT "GOTO [IE.RSRV.OPCODE]" RESERVED ADDRESSING MODE "GOTO [IE.RSRV.ADDRESS]" INTERRUPT FAULT "GOTO [IE.INT.FAULT]" DIE! "MACHINE CHECK [MCHK.CANT.GET.HERE]" .bin